AIC Microsystems Selects Teradyne Audio DAC Test

By TechSecurityChina.com Editor
March 18, 2004

Teradyne, Inc. announced AIC Microsystems Co., Ltd., a supplier of highly integrated system-on-a-chip (SOC) solutions in the multimedia consumer markets, has selected Teradyne to test a next-generation Audio DAC (Digital to Analog Converter).

AIC’s selection of Teradyne, in a competitive design win, was based on the mixed-signal test capability of the Catalyst test system for characterization, the economics of the J750 test system for production testing and Teradyne’s local applications support. With full spectrum instrumentation, Catalyst delivers full test coverage for high performance design verification for a wide range of applications and the J750 architecture is designed to offer the lowest cost of test in a production environment.

Catalyst dominates the SOC market with test capabilities for DSL, wireless, microwave and power management applications. With more than 4,000 individual users worldwide, Catalyst’s IMAGE(TM) programming system is the most widely used ATE software environment. Catalyst currently offers wireless devices, quad-site testing, providing the best test economics and most complete array of analog instrumentation. When a cell call is placed, or a PC, printer, scanner, pager, or DVD is utilized, Catalyst tested ICs make it happens.

The J750’s high-throughput parallel test capability provides as high as 95% parallel test efficiency for up to 32 devices. The zero footprint system delivers up to 1,024 I/O channels contained in a test head, and offers a suite of options, including the Converter Test Option, Memory Test Option, Redundancy Analysis, and Mixed Signal Option, that broaden the range of testing capabilities. The system also features IG-XL test software that combines the power and performance of the latest PC technology and Windows NT operating system with the familiarity of standard Windows productivity tools, such as Microsoft Excel and Visual Basic. The J750’s small footprint and high parallel test throughput provide the most economical approach to testing complex VLSI devices with embedded memory and analog cells.

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