Cadence Tackles Wireless Design With SMIC

By TechSecurityChina.com Editor
November 13, 2006

Cadence Design Systems (CDNS) and Semiconductor Manufacturing International Corporation (SMIC) have announced a new collaboration to deliver the Cadence Radio-Frequency Design Methodology Kit to the China RF IC design market.

SMIC will develop process-design kits (PDKs) that will support the Cadence RF Design Methodology Kit and will validate the PDKs in a test chip by the end of 2006.

The CMOSRF 180-nanometer PDKs will be available to customers by the end of 2006. Cadence and SMIC will jointly deliver RFIC methodology workshops and provide RF Kit Applicability Consulting to Chinese RF designers.

With this collaboration, wireless chip designers in China will have the necessary tools to achieve shorter, more predictable design cycles by ensuring that silicon performance matches design intent. As part of their joint effort, both companies will also offer applicability training and workshops.

”There are many techniques peculiar to wireless. A design kit with recommendations on methodologies and tools is a benefit to our customers. Our collaboration with Cadence on RF design will help customers in China design and deliver high-quality RF devices,” said Paul Ouyang, vice president of Design Services at SMIC. ”The combination of the Cadence advanced full-custom RF IC design technologies, RF Methodology Kit with SMIC’s RF CMOS process technologies will offer the highest levels of quality and productivity enabling silicon success for our customers. We look forward to continuing our close partnership with Cadence to provide to our mutual customer a joint RF IC solution based on 130-nanometer and 90-nanometer RF CMOS processes.”

The RF Methodology Kit includes an 802.11 b/g WLAN transceiver reference design, a full suite of block-, chip-, and system-level test benches, simulation setups, test plans, and applicability training on the RF design and analysis methodologies. The kit focuses on top-down RF IC design and full-chip verification and addresses behavioural modelling, circuit simulation, layout, parasitic extraction and re-simulation, and inductor synthesis. It also focuses on IC verification within a system context, leveraging system-level models and test benches for use by designers in the IC environment.











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